Integrated circuits (ICs) typically include one or more devices (e.g., transistors, diodes, capacitors, etc.) formed in a semiconductor substrate. In Silicon on insulator (SOI) technology, the semiconductor substrate includes a buried layer of insulation. SOI substrates are preferable in some applications because the buried layer of insulation electrically isolates the devices, which leads to improved device characteristics. For example, benefits of SOI technology include lower parasitic capacitance, reduced cross-talk between neighboring devices, and decreased likelihood of a latchup condition during operation of the devices.
Known techniques for forming SOI substrates include SIMOX (Separation by Implantation of Oxygen) techniques and SmartCut techniques. In either process, a surface of a semiconductor substrate is oxidized to form a dielectric layer that will ultimately serve as the buried layer of insulation. Subsequently, porous layers are formed within the substrate. In the case of SmartCut, the porous layer is a layer of implanted hydrogen and wafer bonding is applied and the substrate is separated along the implanted hydrogen. In the case of SIMOX, the porous layer is a layer of implanted oxygen. Thus, the ion implantation and wafer bonding steps associated with these processes introduce expense and complexity in the substrate manufacturing process.
One alternative technique for forming an SOI substrate that does not involve ion implantation and wafer bonding is referred to as a Silicon on nothing (SON) technique. In SON technology, rather than sing an oxide material (e.g., SiO2) as the buried insulator layer, unfilled voids are provided in the substrate. These unfilled voids can be used to provide a buried insulator with favorable dielectric properties because the air within the voids has a lower dielectric constant than oxide materials. However, SON techniques are limited because increasing the size of the unfilled void comes at the expense of mechanical stability of the substrate. For example, if a void occupies a substantial portion of the chip area, only the lateral edges of the substrate support the upper portion of the substrate. As a result, the mechanical stability of the substrate is compromised.